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  myson technology MTD907 ethernet encoder/decoder and 10baset transceiver with built-in waveform shaper this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. MTD907 revision 4.5 01/23/1997 1/ 14 features ? pin-out and functionally compatible with level one lxt907. ? built-in utp waveform shaping function - no external filters required. ? integrated manchester encoder/decoder. ? 10base-t compliant transceiver and aui transceiver. ? full duplex cap ability. ? automatic and manual interface selection (aui/tp). ? automatic tp polarity detection and correction. ? heartbeat enable/disable function and jabber disable function. ? drives 4 led status indicators. general description MTD907 is an integrated ethernet endec and 10base-t transceiver with built-in utp transmission waveform shaping function. the integrated encoder/decoder conforms to ieee802.3 standards and provides all needed active circuitry with which to interface the majority of ieee802.3-conforming controllers to either the 10base-t media or attachment unit interface (aui). the functions provided by MTD907 include manchester encoding/decoding, jabber detection, automatic media selection, reception squelch and transmission waveform shaping, automatic utp polarity detection and correction for the utp media. block diagram collision logic led/status logic remote signaling test logic xcal osc media selection and control waveform shaping linktest polarity detect amp ac/dc squelch amp ac/dc squelch reference circuit mode control manchester coder/ decoder md0, md1 txc txc, txe crs, rxc, rxd col, jab dsq ledr, ledl, ledc, ledt jab, plr rld, rjab, rcmpt tst trst lbk aut pau lte x2 x1 dip, cip din, cin dop don rdp rdn nth tpa, tpb tna, tnb
myson technology MTD907 MTD907 revision 4.5 01/23/1997 2 / 14 1.0 pin connection 44-pin plcc MTD907 44-pin plcc rdn rdp dsq tnb tna vdd2 vss2 tp a tp b plr rjab rld lte jab tst txc txd txe x1 x2 col aut md1 md0 nth cin cip vdd1 don dop din dip pau ledr ledt ledl ledc lbk vss1 trst rcmpt rxd crs rxc 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 1.0 pin descriptions no symbol i/o name description 1 34 vdd1 vdd2 - positive power supply +5 volt power supplies. 2 3 cip cin i i collision input pair aui transceiver ci circuit differential input pair. 4 nth i normal threshold active high input, selects normal tp input threshold; when nth=0, the tp input threshold is reduced 4.5db. 5 6 md0 md1 i i mode selection mode selection pins. determines controller compatibility mode: mode 00 is for amd, 01 for intel, 10 for fujitsu, 11 for nsc. 7 rld o remote link down active high output. signifies when the remote port is in link down condition. 8 lte i link test enabler active high input. enables the link test when high; when low, disables the tp link test. 9 jab o jabber indicator active high output. high output indicates jabber condition. 10 tst i test active high input internally pulled low. this pin is used in test mode only. 11 txc o transmit clock 10 mhz clock output. should be directly connected to the controller to synchronize transmission operation. 12 txd i transmit data input signal, nrz data from the controller. 13 txe i transmission enabler active high input. enables data transmission and begins jabber timer; should be synchronized with txc by the controller. 14 15 x1 x2 o i crystal oscillator built-in crystal oscillator. a 20 mhz crystal must be connected across these 2 pins or an external clock must be applied to x2 with x1 left open. 16 col o collision detection output signal; drives controller collision detection input.
myson technology MTD907 MTD907 revision 4.5 01/23/1997 3 / 14 17 aut i automatic port selection active high input. when active, MTD907 defaults to the aui port if the tp link test fails. if driven low, the port selection is determined by the pau pin. 18 ledr/ jabdis o i receive led, disable jabber active low output driver for receiving the led indicator. the led 'on ? time is extended by at least 80 ms. when externally tied or driven low, disables the internal jabber timer. 19 ledt/ pwdn o i transmit led, power down active low output driver for led transmission indicator. the led 'on ? time is extended by at least 80ms. when externally tied or driven low, forces MTD907 into power-down state. 20 ledl/ lpss o i link led, link pass active low output driver for link integrity led indicator. when externally tied or driven low, forces MTD907 into 'link pass' state. 21 ledc/ fdx o i collision led, full duplex active low output driver for collision indicator led. the led on time is extended by at least 80 ms. when externally tied low, enables MTD907 for full duplex operation by disabling internal tp loopback and tp collision detection functions. 22 lbk i loopback active high input; enables internal loopback mode. 23 33 vss1 vss2 - negative power supply power supply ground. 24 trst i test mode reset active high test mode reset signal. only recognized in test mode (tst pin high) and internally pulled low. 25 rcmpt o remote compatible active high output; indicating tp transceiver at the remote end is compatible with remote signaling. 26 rxd o received data output signal; recovers received data. should be connected directly to controller. 27 crs o carrier sense output signal; detects incoming network traffic. should be connected directly to controller. 28 rxc o received clock output signal; recovers received clock. should be connected directly to controller. 29 rjab o remote jabber active high output signal; indicates when the remote end is in jabber state. 30 plr o polarity reversal active high output signal; indicates when the tp polarity is reversed. 31 32 35 36 tpb tpa tna tnb o o o o twisted-pair transmission pairs a & b two differential driver pairs (a and b) for the tp cable. the outputs are pre-equalized, thus no external filters are required. the tpx pins and tnx pins must be shorted together with a 24.9 w 1% to match the 100 w tp impedance. 37 dsq i disable sqe active high input. when driven high, selects MTD907 for hub/switch/repeater operation by disabling signal quality test (heartbeat). 38 39 rdp rdn i i receive data input pair (tp) differential input pair for tp cable. the reception filter is integrated on-chip. no external filter is required. 40 pau i select port/aui recognized only if the aut pin is low. pau=1 selects aui port, pau=0 selects tp port. it is recommended that you tie this pin to ground if driving aut pin high. 41 42 dip din i i aui reception pair differential input pair from the aui transceiver di circuit. 43 44 dop don o o aui transmission pair differential output pair to the aui transceiver do circuit.
myson technology MTD907 MTD907 revision 4.5 01/23/1997 4 / 14 2.0 controller compatibility mode descriptions mode controllers: md0 md1 1 advanced micro devices am7990 or compatible controllers. 0 0 2 intel 82586 or 82596, or compatible controllers. 0 1 3 fujitsu mb86950 or mb86960, seeq 8005 or compatible continuous clock-type controllers. 1 0 4 national semiconductor 8390, ti tms380c26 or compatible controllers. 1 1 3.0 absolute maximum ratings dc supply voltage (vcc) -0.5v to +7v dc input voltage (vin) -0.5v to vcc+0.5v storage temperature -65 o c to 150 o c operating temperature 0 o c to 70 o c 4.0 operating conditions parameter symbol min typ max unit test conditions power supply voltage vcc 4.75 5 5.25 v operating temperature top 0 - 70 o c icc - 35 55 ma idle icc - 60 80 ma transmitting on tp icc - 50 70 ma transmitting on aui supply current icc - 3 6 ma power-down mode 5.0 electrical characteristics (under operating conditions) parameter symbol min typ max unit test conditions input low voltage v il - - 0.8 v input high voltage v ih 2.0 - - v output low voltage v ol - - 0.4 v iol=1.6ma output high voltage v oh 2.4 - - v iol=40ua output low voltage (led) v ol - - 0.7 v iol=10ma t r - 3 12 ns cload=20pf output rise time (txc, rxc) t r - 2 8 ns ttl load t f - 3 12 ns cload=20pf output fall time (txc, rxc) t f - 2 8 ns ttl load x2 rise time (external clock) - - - 10 ns x2 duty cycle (external clock) - - 50/50 40/60 % 6.0 aui electrical characteristics (under operating conditions) parameter symbol min typ max unit test conditions input low current i l - - -700 ua input high current i h - - 500 ua differential output voltage v od 550 - 1200 mv differential squelch threshold v ds 150 220 350 mv 5 mhz square wave
myson technology MTD907 MTD907 revision 4.5 01/23/1997 5 / 14 7.0 tp electrical characteristics (under operating conditions ) parameter symbol min typ max unit test conditions transmit output impedance zout - 5 - w peak differential output voltage vod 3.3 3.5 3.7 v load=100 w transmit timing jitter addition - - 6.4 10 +/- ns internal mau transmit timing jitter added by mau and pls sections - - 3.5 5.5 +/- ns after ieee 802.3- specified tp line model receive input impedance zin - 20 - k w between input pairs vds 300 420 585 mv 5mhz square wave input, nth=1 differential squelch threshold vds 180 250 345 mv 5mhz square wave input, nth=0 8.0 switching characteristics (under operating conditions) jabber timing: parameter symbol min typ max unit maximum transmission time before jabber - 20 - 150 ms unjab time - 250 - 750 ms link integrity pulse timing: parameter symbol min typ max unit link loss time - 63 - 64 ms transmit link integrity timing - 8 - 24 ms receive link integrity pulse timing - 3.1 - 63 ms start-of-frame timing, aui parameter symbol min typ max unit decoder acquisition time t data - 700 1100 ns cd turn-on delay t cd - 50 200 ns start-of-frame timing, tp parameter symbol min typ max unit decoder acquisition time t data - 1000 1700 ns cd turn-on delay t cd - 400 550 ns rxc timing parameter symbol typ mode 1 mode 2 mode3 mode 4 unit receive data setup from rxc t rds min. 43 30 30 30 ns receive data hold from rxc t rdh min. 10 30 30 30 ns rxc shut-off delay from crs assertion t sws typ. - - +/-100 - ns rxc hold after crs turn-off t rch - 8 1 - 8 bt rxd data through delay t rd max. 400 375 375 375 ns crs turn-off delay t crsoff max. 500 475 475 475 ns rxc switching delay after cd off t swe typ. - - 120 - ns
myson technology MTD907 MTD907 revision 4.5 01/23/1997 6 / 14 transmission timing parameter symbol min typ max unit txe setup from txc t ehch 22 - - ns txd setup from txc t dach 22 - - ns txe hold from txc t chel 5 - - ns txd hold from txc t chdu 5 - - ns transmission start-up delay, aui t stud - 200 450 ns transmission start-up delay, tp t stud - 350 450 ns transmission through delay, aui t tpd - - 300 ns transmission through delay, tp t tpd - - 350 ns col and loopback timing parameter symbol min typ max unit col turn-on delay t cold - - 500 ns col turn-off delay t coloff - - 500 ns col (sqe) delay after txe off t sqed 0.65 - 1.6 us col (sqe) pulse duration t sqep 500 - 1500 ns lbk setup from txe t kheh 10 25 - ns lbk hold after txe t khel 10 0 - ns 9.0 timing diagram mode 1, rxc - start of frame timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 tpip/tpin or dip/din crs rxc rxd t data 1 0 1 0 1 0 1 1 1 0 1 1 0 t rds t rdh t crs mode 1, rxc - end of frame timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff t rch tpip/tpin or dip/din crs rxc rxd
myson technology MTD907 MTD907 revision 4.5 01/23/1997 7 / 14 mode 1, transmission timing t ehch t stud t dsch t tpd t chel txe txc txd tpo t chdu mode 1, collision detection timing t cold t coloff ci col mode 1, hbt/ci output timing t sqed t sqep txe col mode 1, loopback timing t khel t caea t kheh lbk txe crs mode 2, rxc - start of frame timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 tpip/tpin or dip/din crs rxc rxd t data 1 0 1 0 1 0 1 1 1 0 1 1 0 t rds t rdh t crs
myson technology MTD907 MTD907 revision 4.5 01/23/1997 8 / 14 mode 2, rxc - end of frame timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff t rch tpip/tpin or dip/din crs rxc rxd mode 2, transmission timing t ehch t stud t dsch t tpd t chel txe txc txd tpo t chdu mode 2, collision detection timing t cold t coloff ci col mode 2, hbt/ci output timing t sqed t sqep txe col mode 2, loopback timing t khel t caea t kheh lbk txe crs
myson technology MTD907 MTD907 revision 4.5 01/23/1997 9 / 14 mode 3, rxc - start of frame timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 tpip/tpin or dip/din crs rxc rxd t data 1 0 1 0 1 0 1 1 1 0 1 1 0 t rds t rdh t crs t sws generated form tclk recovered form input data stream mode 3, rxc - end of frame timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff t swe tpip/tpin or dip/din crs rxc rxd recovered clock generated from txc mode 3, transmission timing t ehch t stud t dsch t tpd t chel txe txc txd tpo t chdu mode 3, collision detection timing t cold t coloff ci col
myson technology MTD907 MTD907 revision 4.5 01/23/1997 10 / 14 mode 3, hbt/ci output timing t sqed t sqep txc col mode 3, loopback timing t khel t caea t kheh lbk txe crs mode 4, rxc - start of frame timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 tpip/tpin or dip/din crs rxc rxd t data 1 0 1 0 1 0 1 1 1 0 1 1 0 t rds t rdh t crs mode 4, rxc - end of frame timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff t rch tpip/tpin or dip/din crs rxc rxd
myson technology MTD907 MTD907 revision 4.5 01/23/1997 11 / 14 mode 4, transmission timing t ehch t stud t dsch t tpd t chel txe txc txd tpo t chdu mode 4, collision detection timing t cold t coloff ci col mode 4, hbt/ci output timing t sqed t sqep txe col mode 4, loopback timing t khel t caea t kheh lbk txe crs 10.0 functional description MTD907 is an ethernet endec and 10baset transceiver with a built-in waveform shaper that performs the media attachment unit (mau) and physical layer signaling (pls) functions as defined in the ieee802.3 specification. MTD907 can function as either a pls-only device interfacing a supported controller to an aui cable or as an integrated pls/mau interfacing a supported controller to the tp cable. in the following functional descriptions, aii functions are defined as seen from the controller side of the interface. controller compatibility MTD907 is configurable for interfacing with common industrial standard ethernet controllers. the mode selection pins, md0 and md1, provide the mode configuration capability as tabulated in section 2.0. the timing specification of different controller modes is specified in section 8.0 ? s rxc timing. applicable timing diagrams for each of the supported controller modes are included in section 9.0.
myson technology MTD907 MTD907 revision 4.5 01/23/1997 12 / 14 transmission function MTD907 samples txd data from the controller at the rising edge of the txc signal and then performs the manchester encoding on the input data stream. the encoded data is then transmitted through either the aui port or the tp cable network . the built-in waveform-shaping circuits produce pre-distorted tp output waveform comforming to the jitter template specified in ieee802.3. no external filter is required in MTD907 applications. if lte is enabled and the tp port is selected as the network media, MTD907 transmits link integrity test pulses at regular intervals during idle periods. due to its voltage drive and tp output drivers' low output impedence, the driving end source resistance is decided by external resistors. jabber control function the jabber control function of MTD907 closely follows the ieee 802.3 specification. the MTD907 built-in watchdog timer prevents the dte from continuous transmission. when the txe input is asserted for longer than the time limit, both transmission and loopback functions are disabled, and the jab output pin will be asserted. once MTD907 enters the jabber state, it will exit it only if the txe signal remains idle for a period of 250-750ms. the jabber function of MTD907 can be disabled by externally pulling the ledr pin low. sqe function MTD907 supports the signal quality error (sqe) function, which can be disabled through dsq input. if the sqe function is enabled (dsq=0), MTD907 will transmit the sqe signal after every successful 10baset transmission. this sqe signal will be a 10 +/- 5 bit time assertion of the col output pin. if the aui port is selected as the transmission media, the sqe is determined by the external mau. when using MTD907 in hub or switch applications, the sqe function must be disabled (dsq=1). reception function MTD907 ? s reception function recovers both the clock and data from the incoming manchester-encoded data stream from either the aui or tp port. the recovered clock and data are sent to the controller through the rxc and rxd pins, respectively. internal filter and squelch functions are integrated in MTD907 in order to discriminate noise from valid tp signals. no external reception filter is needed. if the incoming signal from either the aui or tp input exceeds the squelch requirements, the crs pin will be asserted and internal timing recovery circuits will be activated. a fast lock-on pll will typically lock on to the input signal in 5-bit time. if the input signal drops below the squelch threshold or signal transitions are absent for 8-bit time (typical), the internal circuit will return to its idle state. tp interface polarity correction function the MTD907 tp interface polarity correction function detects and corrects tp polarity error using both tp link pulses and end-of-frame data. the tp polarity is internally decided as being reversed only if 8 consecutive link pulses or end-of-frame data are received with a polarity opposite to the expected polarity. upon detecting tp polarity reversal, MTD907 will automatically exchange the received tp data polarity. this correction function is always active. collision detection function the collision detection function is applicable only if MTD907 is used as pls/mau in a standard 10baset network. a collision is detected if valid data is present simultaneously on both tp transmission and tp reception circuits. MTD907 reports this to the controller via the assertion of the col output. if MTD907 is used as pls only, i.e. external mau, then the collision detection is based on valid signals from the aui port. if MTD907 is configured to function as a full-duplex tp transceiver by externally pulling the ledc pin low, the collision detection function for tp will be disabled internally. also, if the MTD907 lbk pin is driven high, all collision function is disabled. loopback function
myson technology MTD907 MTD907 revision 4.5 01/23/1997 13 / 14 MTD907 has 4 different loopback modes. if the tp port and half-duplex mode are selected, MTD907 provides the normal loopback function as defined in 10baset standards. if the tp port and full-duplex mode are selected, the internal loopback is disabled, allowing external loopback through tp ports. if the aui interface is selected and lbk=0, the external aui loopback mode is in effect. if lbk is driven high, the internal collision detection function is disabled, and the transmission data is forced to loop back through internal manchester endec with disregard as to which interface port is selected. link integrity test the MTD907 link integrity test is implemented as specified in ieee802.3 10baset standards. this function is enabled when input pin 8 (lte) is driven high. while lte=1, MTD907 will recognize link integrity pulses received in absence of a valid tp data packet. if both link integrity pulses and tp data packets are not detected within 65-66ms, MTD907 will enter a link-fail state and will disable the transmission and normal loopback functions. after it enters such a state, MTD907 will exit the link-fail state if one valid tp packet or 2 or more link integrity pulses are received. link integrity pulses received within an interval of 4ms will be ignored by MTD907. remote signaling the link integrity pulses transmitted by MTD907 include encoded local status information by varying the link pulse intervals. this feature is implemented in such a way that MTD907 is compatible with any chip that uses the same signaling scheme, such as many of the level one products. three different pieces of status information are encoded and are described as follows. local link-down is encoded as link pulse interval sequences of 10ms-15ms-20ms. local jabber is encoded as link pulse interval sequences of 10ms-20ms-15ms. remote-signaling capability is encoded as a link pulse interval sequence of 10ms-20ms. MTD907 will detect and decode link pulses, thus encoding and reporting them through the rld, rjab and rcmpt output pins, respectively. 11.0 comparison of MTD907 and level one lxt901/lxt907 waveform synthesis method the main difference between MTD907 and level one lxt901/lxt907 is the waveform synthesis method used. level one products use a table-look-up method with a 5-bit dac operating at 70mhz. MTD907 uses a delay cell based 16-tab fir filter operating at 160mhz to synthesize the pre-distorted transmission waveforms required by 10baset standards with much refined waveform. mode1 and mode4 end-of-frame rxc timing eight end-of-frame rxc pulses are provided for better controller interfacing for mode1 and mode 4 style timing. MTD907 vs lxt901 these 2 devices share the same functionality except for pin 37. lxt901 uses this pin as a utp/stp selection input while MTD907 uses this pin as dsq to disable or enable the built-in sqe function. for typical lxt901 utp applications, this pin is tied high in order to select utp interface. for these applications, MTD907 should be a drop-in replacement for lxt901 if the attached controller does not check the sqe signal. MTD907 vs lxt907 the only noticeable difference between these 2 devices is that when lxt907 enters the power-down mode, it will drive the ledl low periodically, while MTD907 disables all output pins once forced into the power-down mode.
myson technology MTD907 MTD907 revision 4.5 01/23/1997 14 / 14 12.0 applications please see the attached application schematics. 13.0 package dimension 44 pin plcc unit: inch pin #1 hole 0.653 +/-0.003 0.690 +/-0.005 0.6902 +/-0.005 0.653 +/-0.003 0.045*45 0 0.180 max. 0.020 min. 0.610 +/-0.02 0.500 0.070 0.070 7 0 typ. 0.010 0.050 typ. 0.013~0.021 typ. 0.026~0.032 typ.


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